IP PortfolioVideo, imaging and audio

Video, imaging, display and audio

Image signal processing, video codecs, display controllers and pipelines, 2D/3D graphics helpers, audio codecs and DSP, computer vision primitives.

Blocks 107Implemented 15Families 8FPGA + ASIC 107

isp

21 blocks · 10 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_isp_blc	Black level correction	simulated	FPGA + ASIC	Easy
of_mm_isp_dpc	Defect pixel correction	simulated	FPGA + ASIC	Medium
of_mm_isp_lsc	Lens shading correction	simulated	FPGA + ASIC	Medium
of_mm_isp_demosaic	Bayer demosaic	simulated	FPGA + ASIC	Medium
of_mm_isp_3a_stats	Auto exposure, white balance and focus statistics	simulated	FPGA + ASIC	Medium
of_mm_isp_awb_gain	White balance gain and colour correction matrix	simulated	FPGA + ASIC	Easy
of_mm_isp_gamma	Gamma and tone curve LUT	simulated	FPGA + ASIC	Easy
of_mm_isp_hdr_merge	Multi-exposure HDR merge	planned	FPGA + ASIC	Hard
of_mm_isp_tonemap	Local tone mapping	planned	FPGA + ASIC	Hard
of_mm_isp_nr2d	Spatial noise reduction	simulated	FPGA + ASIC	Medium
of_mm_isp_nr3d	Temporal noise reduction	planned	FPGA + ASIC	Hard
of_mm_isp_sharpen	Sharpening and edge enhancement	planned	FPGA + ASIC	Easy
of_mm_isp_csc	Colour space converter	simulated	FPGA + ASIC	Easy
of_mm_isp_scaler	Polyphase image scaler	simulated	FPGA + ASIC	Medium
of_mm_isp_ldc	Lens distortion correction and dewarp	planned	FPGA + ASIC	Hard
of_mm_isp_eis	Electronic image stabilization	planned	FPGA + ASIC	Hard
of_mm_isp_stereo_depth	Stereo depth engine	planned	FPGA + ASIC	Very hard
of_mm_isp_optical_flow	Dense optical flow engine	planned	FPGA + ASIC	Very hard
of_mm_isp_tof_depth	Indirect ToF depth processing	planned	FPGA + ASIC	Hard
of_mm_isp_pipeline	Integrated camera ISP pipeline	planned	FPGA + ASIC	Very hard
of_mm_isp_raw_compress	Raw image compression	planned	FPGA + ASIC	Medium

16 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_vid_h264_enc	H.264/AVC encoder	planned	FPGA + ASIC	Very hard
of_mm_vid_h264_dec	H.264/AVC decoder	planned	FPGA + ASIC	Very hard
of_mm_vid_h265_enc	H.265/HEVC encoder	planned	FPGA + ASIC	Very hard
of_mm_vid_h265_dec	H.265/HEVC decoder	planned	FPGA + ASIC	Very hard
of_mm_vid_h266_dec	H.266/VVC decoder	planned	FPGA + ASIC	Very hard
of_mm_vid_h266_enc	H.266/VVC encoder	planned	FPGA + ASIC	Very hard
of_mm_vid_vp9_dec	VP9 decoder	planned	FPGA + ASIC	Very hard
of_mm_vid_vp9_enc	VP9 encoder	planned	FPGA + ASIC	Very hard
of_mm_vid_av1_dec	AV1 decoder	planned	FPGA + ASIC	Very hard
of_mm_vid_av1_enc	AV1 encoder	planned	FPGA + ASIC	Very hard
of_mm_vid_jpeg	JPEG encoder and decoder	planned	FPGA + ASIC	Medium
of_mm_vid_jpegxs	JPEG XS codec	planned	FPGA + ASIC	Hard
of_mm_vid_jpeg2000	JPEG 2000 codec	planned	FPGA + ASIC	Very hard
of_mm_vid_png_deflate	Lossless image codec (PNG)	planned	FPGA + ASIC	Medium
of_mm_vid_me	Motion estimation engine	planned	FPGA + ASIC	Hard
of_mm_vid_transcode_scaler	Multi-output transcoding scaler	planned	FPGA + ASIC	Medium

12 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_disp_ctrl	Display controller	planned	FPGA + ASIC	Hard
of_mm_disp_compositor	Hardware compositor	planned	FPGA + ASIC	Hard
of_mm_disp_hdr_meta	HDR metadata processor	planned	FPGA + ASIC	Hard
of_mm_disp_frc	Frame rate converter	planned	FPGA + ASIC	Very hard
of_mm_disp_dsc_enc	VESA DSC encoder	planned	FPGA + ASIC	Hard
of_mm_disp_dsc_dec	VESA DSC decoder	planned	FPGA + ASIC	Hard
of_mm_disp_tcon	Panel timing controller (TCON)	planned	FPGA + ASIC	Medium
of_mm_disp_overdrive	LCD overdrive	planned	FPGA + ASIC	Medium
of_mm_disp_local_dimming	Local dimming controller	planned	FPGA + ASIC	Hard
of_mm_disp_oled_comp	OLED compensation and burn-in mitigation	planned	FPGA + ASIC	Hard
of_mm_disp_gamut	Display gamut mapping and 3D LUT	planned	FPGA + ASIC	Medium
of_mm_disp_dither	Spatial-temporal dither	planned	FPGA + ASIC	Easy

6 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_gfx_blitter	2D blitter	planned	FPGA + ASIC	Medium
of_mm_gfx_alpha_blend	Alpha blending engine	planned	FPGA + ASIC	Easy
of_mm_gfx_rotate	Image rotation and mirroring	planned	FPGA + ASIC	Medium
of_mm_gfx_font	Font and glyph renderer	planned	FPGA + ASIC	Medium
of_mm_gfx_vector	2D vector graphics rasterizer	planned	FPGA + ASIC	Hard
of_mm_gfx_fbc	Frame buffer compression	planned	FPGA + ASIC	Hard

17 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_cv_cnn_pre	CNN preprocessing engine	planned	FPGA + ASIC	Medium
of_mm_cv_cnn_post	CNN postprocessing engine	planned	FPGA + ASIC	Medium
of_mm_cv_fast_orb	FAST corner and ORB descriptor engine	planned	FPGA + ASIC	Hard
of_mm_cv_sift_like	Scale-space feature extractor	planned	FPGA + ASIC	Very hard
of_mm_cv_harris	Harris corner detector	planned	FPGA + ASIC	Medium
of_mm_cv_hough	Hough transform engine	planned	FPGA + ASIC	Medium
of_mm_cv_ccl	Connected components labeling	planned	FPGA + ASIC	Medium
of_mm_cv_histogram	Image histogram and equalization	planned	FPGA + ASIC	Easy
of_mm_cv_morph	Morphology engine	planned	FPGA + ASIC	Easy
of_mm_cv_edge	Edge detection engine	simulated	FPGA + ASIC	Medium
of_mm_cv_conv_filter	Generic 2D convolution filter	simulated	FPGA + ASIC	Easy
of_mm_cv_pyramid	Image pyramid generator	planned	FPGA + ASIC	Medium
of_mm_cv_integral	Integral image engine	planned	FPGA + ASIC	Easy
of_mm_cv_template_match	Template matching engine	planned	FPGA + ASIC	Medium
of_mm_cv_remap_affine	Affine and perspective warp engine	planned	FPGA + ASIC	Medium
of_mm_cv_bgsub	Background subtraction engine	planned	FPGA + ASIC	Medium
of_mm_cv_dvs_events	Event camera stream processor	planned	FPGA + ASIC	Medium

19 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_aud_src	Asynchronous sample rate converter	planned	FPGA + ASIC	Hard
of_mm_aud_eq	Parametric equaliser	planned	FPGA + ASIC	Easy
of_mm_aud_drc	Dynamic range compressor and limiter	planned	FPGA + ASIC	Medium
of_mm_aud_mic_bf	Microphone array beamformer	planned	FPGA + ASIC	Hard
of_mm_aud_aec	Acoustic echo canceller	planned	FPGA + ASIC	Hard
of_mm_aud_ns	Noise suppression	planned	FPGA + ASIC	Medium
of_mm_aud_anc	Active noise cancellation	planned	FPGA + ASIC	Hard
of_mm_aud_kws_fe	Keyword spotting front end	planned	FPGA + ASIC	Medium
of_mm_aud_mixer	Audio mixer and router	planned	FPGA + ASIC	Easy
of_mm_aud_aac_dec	AAC decoder	planned	FPGA + ASIC	Hard
of_mm_aud_opus	Opus codec	planned	FPGA + ASIC	Hard
of_mm_aud_lc3	LC3 codec	planned	FPGA + ASIC	Medium
of_mm_aud_flac_dec	FLAC decoder	planned	FPGA + ASIC	Medium
of_mm_aud_mp3_dec	MP3 decoder	planned	FPGA + ASIC	Medium
of_mm_aud_speech_codec	Telephony speech codec	planned	FPGA + ASIC	Medium
of_mm_aud_spatial	Spatial audio renderer	planned	FPGA + ASIC	Hard
of_mm_aud_loudness	Loudness meter and normalizer	planned	FPGA + ASIC	Easy
of_mm_aud_fir_engine	Audio FIR and convolution engine	planned	FPGA + ASIC	Medium
of_mm_aud_spk_protect	Speaker protection	planned	FPGA + ASIC	Hard

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_xr_timewarp	Asynchronous time warp engine	planned	FPGA + ASIC	Hard
of_mm_xr_foveation	Foveated rendering helper	planned	FPGA + ASIC	Hard
of_mm_xr_passthrough	Video passthrough processor	planned	FPGA + ASIC	Very hard
of_mm_xr_eye_track	Eye tracking image front end	planned	FPGA + ASIC	Hard

12 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_mm_vio_deinterlace	Motion-adaptive deinterlacer	planned	FPGA + ASIC	Hard
of_mm_vio_chroma_resample	Chroma resampler	simulated	FPGA + ASIC	Easy
of_mm_vio_tpg	Video test pattern generator	simulated	FPGA + ASIC	Easy
of_mm_vio_vtg	Video timing generator	simulated	FPGA + ASIC	Easy
of_mm_vio_osd	On-screen display overlay	planned	FPGA + ASIC	Medium
of_mm_vio_frame_buffer	Video frame buffer DMA	planned	FPGA + ASIC	Medium
of_mm_vio_crop_pad	Region of interest crop and pad	planned	FPGA + ASIC	Easy
of_mm_vio_anc	Ancillary data and audio embedder	planned	FPGA + ASIC	Medium
of_mm_vio_st2110	SMPTE ST 2110 video packetizer	planned	FPGA + ASIC	Hard
of_mm_vio_aes67	AES67 audio over IP packetizer	planned	FPGA + ASIC	Medium
of_mm_vio_genlock	Genlock and frame lock	planned	FPGA + ASIC	Medium
of_mm_vio_quality_metrics	Video quality metrics engine	planned	FPGA + ASIC	Medium