IP PortfolioVideo, imaging and audiovision
of_mm_cv_histogram
Image histogram and equalization
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Global and tile-based histogram accumulation with contrast-limited adaptive histogram equalization.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 16 | |
| pix_out | out | AXI4-Stream | 16 |
Standards
No external standard applies.
More in vision
| ID | Block | Maturity |
|---|---|---|
| of_mm_cv_cnn_pre | CNN preprocessing engine | planned |
| of_mm_cv_cnn_post | CNN postprocessing engine | planned |
| of_mm_cv_fast_orb | FAST corner and ORB descriptor engine | planned |
| of_mm_cv_sift_like | Scale-space feature extractor | planned |
| of_mm_cv_harris | Harris corner detector | planned |
| of_mm_cv_hough | Hough transform engine | planned |
| of_mm_cv_ccl | Connected components labeling | planned |
| of_mm_cv_morph | Morphology engine | planned |
| of_mm_cv_edge | Edge detection engine | simulated |
| of_mm_cv_conv_filter | Generic 2D convolution filter | simulated |