IP PortfolioVideo, imaging and audiodisplay
of_mm_disp_ctrl
Display controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Multi-plane frame buffer scan-out with DMA, pixel format conversion, cursor plane and programmable timings driving parallel RGB, MIPI DSI or DisplayPort transmitters.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_out | out | AXI4-Stream | 30 |
Standards
- VESA DMT
- CTA-861-H
More in display
| ID | Block | Maturity |
|---|---|---|
| of_mm_disp_compositor | Hardware compositor | planned |
| of_mm_disp_hdr_meta | HDR metadata processor | planned |
| of_mm_disp_frc | Frame rate converter | planned |
| of_mm_disp_dsc_enc | VESA DSC encoder | planned |
| of_mm_disp_dsc_dec | VESA DSC decoder | planned |
| of_mm_disp_tcon | Panel timing controller (TCON) | planned |
| of_mm_disp_overdrive | LCD overdrive | planned |
| of_mm_disp_local_dimming | Local dimming controller | planned |
| of_mm_disp_oled_comp | OLED compensation and burn-in mitigation | planned |
| of_mm_disp_gamut | Display gamut mapping and 3D LUT | planned |