IP PortfolioVideo, imaging and audioisp

of_mm_isp_csc

Colour space converter

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

Programmable 3x3 matrix with offsets for RGB and YCbCr conversion across BT.601, BT.709 and BT.2020 primaries.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
pix_ininAXI4-Stream30 
pix_outoutAXI4-Stream30 

Standards

  • ITU-R BT.601
  • ITU-R BT.709
  • ITU-R BT.2020

More in isp

IDBlockMaturity
of_mm_isp_blcBlack level correctionsimulated
of_mm_isp_dpcDefect pixel correctionsimulated
of_mm_isp_lscLens shading correctionsimulated
of_mm_isp_demosaicBayer demosaicsimulated
of_mm_isp_3a_statsAuto exposure, white balance and focus statisticssimulated
of_mm_isp_awb_gainWhite balance gain and colour correction matrixsimulated
of_mm_isp_gammaGamma and tone curve LUTsimulated
of_mm_isp_hdr_mergeMulti-exposure HDR mergeplanned
of_mm_isp_tonemapLocal tone mappingplanned
of_mm_isp_nr2dSpatial noise reductionsimulated