IP PortfolioVideo, imaging and audiovision
of_mm_cv_edge
Edge detection engine
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Sobel, Scharr and Canny edge detection with gradient magnitude, direction and hysteresis thresholding.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 8 | |
| pix_out | out | AXI4-Stream | 8 |
Standards
No external standard applies.
More in vision
| ID | Block | Maturity |
|---|---|---|
| of_mm_cv_cnn_pre | CNN preprocessing engine | planned |
| of_mm_cv_cnn_post | CNN postprocessing engine | planned |
| of_mm_cv_fast_orb | FAST corner and ORB descriptor engine | planned |
| of_mm_cv_sift_like | Scale-space feature extractor | planned |
| of_mm_cv_harris | Harris corner detector | planned |
| of_mm_cv_hough | Hough transform engine | planned |
| of_mm_cv_ccl | Connected components labeling | planned |
| of_mm_cv_histogram | Image histogram and equalization | planned |
| of_mm_cv_morph | Morphology engine | planned |
| of_mm_cv_conv_filter | Generic 2D convolution filter | simulated |