Open hardware design platform by Dyber, Inc.
From idea to hardware.
OpenForge is one desktop platform for the whole hardware stack: wafer process and device physics, RTL to GDS with signoff, FPGA, analog and photonics, packaging, PCB, signal integrity, thermal, firmware and fab planning. It runs on open engines, keeps every model auditable, and ships with a foundation IP library of 1,410 catalogued blocks.
Three domains, one project
Chips, light and boards in the same window
Switch domains from the toolbar and the menus, panels and rule decks follow. The project stays the same, so a die's ball map can become a board footprint and a power map can become a thermal load without an export step.
Silicon
Process and device simulation, RTL design and verification, synthesis, place and route, multi-corner timing, DFT, analog and custom layout, and native DRC, LVS and extraction. FPGA flows sit beside the ASIC flow.
- Yosys
- OpenROAD
- OpenSTA
- ngspice
- DEVSIM
- nextpnr
Photonic
Silicon photonics layout from a component library of waveguides, bends, couplers, MMIs, rings and interferometers, with circuit simulation, a waveguide mode solver and GDS output.
- gdsfactory
- MEEP
- soi220
PCB and systems
Schematic and board design with an Altium-compatible keymap, package and 3D-IC, SI/PI and analyzers, thermal and airflow, mechanical CAD, firmware co-simulation and live part data.
- IPC-2581
- ODB++
- Touchstone
- OpenFOAM
- Zephyr
The desktop app
Nineteen workspaces, one window
OpenForge is a native desktop application with docked panels, perspectives per task and a command palette. The engines run as separate processes on Windows, Linux or WSL, and every action is also scriptable.
Tour the workspaces
Where we're pushing
Virtual silicon before you pay for silicon
A respin costs months and a mask set. We are building a chain of simulation from materials to system, calibrated against measured data, so more problems surface before tapeout. It reduces respins. It does not replace silicon, and the tool says so.
Tiers earned by reproducible flows
Every IP block records the highest tier it has earned, from planned to silicon, with the evidence stored next to it. 26 blocks have already met timing on a routed FPGA netlist.
Models you can audit
Each model cites its correlation or standard and states its validity range. Placeholders and assumptions are labelled in the interface, never hidden in a number.
Native DRC, LVS and extraction
Rust engines read GDS, DEF/LEF and SPICE, work across open PDKs, and accept any process through a tech file you keep locally.
OpenForge Foundation IP
1,410 blocks, planned in the open
From adders and FIFOs to RISC-V cores, NPUs, SerDes, radar DSP and qubit control. Every block has a datasheet page, a target list and an honest maturity tier. Select a category to open it.
Build the open stack with us
Foundries, IP integrators and design teams can join the partner program ahead of general release.
Become a partner