IP PortfolioVideo, imaging and audiovideo_processing
of_mm_vio_vtg
Video timing generator
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Programmable horizontal and vertical sync, blanking and active video timing with detection mode for incoming video.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| hsync | out | serial | 1 | |
| vsync | out | serial | 1 | |
| de | out | serial | 1 |
Standards
- VESA CVT
- VESA DMT
- CTA-861-H
More in video_processing
| ID | Block | Maturity |
|---|---|---|
| of_mm_vio_deinterlace | Motion-adaptive deinterlacer | planned |
| of_mm_vio_chroma_resample | Chroma resampler | simulated |
| of_mm_vio_tpg | Video test pattern generator | simulated |
| of_mm_vio_osd | On-screen display overlay | planned |
| of_mm_vio_frame_buffer | Video frame buffer DMA | planned |
| of_mm_vio_crop_pad | Region of interest crop and pad | planned |
| of_mm_vio_anc | Ancillary data and audio embedder | planned |
| of_mm_vio_st2110 | SMPTE ST 2110 video packetizer | planned |
| of_mm_vio_aes67 | AES67 audio over IP packetizer | planned |
| of_mm_vio_genlock | Genlock and frame lock | planned |