IP PortfolioVerification IPamba bus vip
of_vip_chi_mon
AMBA CHI monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
CHI link and protocol monitor decoding flits on REQ, RSP, SNP and DAT channels, checking link credits, transaction flows and cache state transitions.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 1024 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- AMBA CHI
More in amba bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_axi4_mon | AMBA AXI4 monitor and protocol checker | simulated |
| of_vip_axi4_bfm | AMBA AXI4 bus functional model and agent | simulated |
| of_vip_axil_mon | AMBA AXI4-Lite monitor and protocol checker | simulated |
| of_vip_axil_bfm | AMBA AXI4-Lite bus functional model and agent | simulated |
| of_vip_axis_mon | AMBA AXI4-Stream monitor and protocol checker | simulated |
| of_vip_axis_bfm | AMBA AXI4-Stream bus functional model and agent | simulated |
| of_vip_ahb_mon | AMBA AHB monitor and protocol checker | simulated |
| of_vip_ahb_bfm | AMBA AHB bus functional model and agent | simulated |
| of_vip_apb_mon | AMBA APB monitor and protocol checker | simulated |
| of_vip_apb_bfm | AMBA APB bus functional model and agent | simulated |