AMBA AHB monitor and protocol checker

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

AHB5 and AHB-Lite monitor checking HTRANS sequences, burst address increments and wrap, HREADY wait states, two-cycle error responses and locked transfers.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
tap	in	parallel	128	Observed interface signals
txn	out	AXI4-Stream	128	Decoded transactions for scoreboards

Standards

AMBA AHB5

More in amba bus vip

ID	Block	Maturity
of_vip_axi4_mon	AMBA AXI4 monitor and protocol checker	simulated
of_vip_axi4_bfm	AMBA AXI4 bus functional model and agent	simulated
of_vip_axil_mon	AMBA AXI4-Lite monitor and protocol checker	simulated
of_vip_axil_bfm	AMBA AXI4-Lite bus functional model and agent	simulated
of_vip_axis_mon	AMBA AXI4-Stream monitor and protocol checker	simulated
of_vip_axis_bfm	AMBA AXI4-Stream bus functional model and agent	simulated
of_vip_ahb_bfm	AMBA AHB bus functional model and agent	simulated
of_vip_apb_mon	AMBA APB monitor and protocol checker	simulated
of_vip_apb_bfm	AMBA APB bus functional model and agent	simulated
of_vip_ace_mon	AMBA ACE monitor and protocol checker	planned