AMBA AXI4-Lite bus functional model and agent

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

AXI4-Lite master and slave agents for register access with randomized handshake delays and a register-model adapter.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
m_axil	out	valid-qualified bus	128
s_axil	in	valid-qualified bus	128

Standards

AMBA AXI4-Lite

Basis projects

Permissive open projects the implementation may build on.

cocotbext-axi (MIT)
cocotb (BSD-3-Clause)

Notes

Implemented as of_vip_axil_master and of_vip_axil_slave.

More in amba bus vip

ID	Block	Maturity
of_vip_axi4_mon	AMBA AXI4 monitor and protocol checker	simulated
of_vip_axi4_bfm	AMBA AXI4 bus functional model and agent	simulated
of_vip_axil_mon	AMBA AXI4-Lite monitor and protocol checker	simulated
of_vip_axis_mon	AMBA AXI4-Stream monitor and protocol checker	simulated
of_vip_axis_bfm	AMBA AXI4-Stream bus functional model and agent	simulated
of_vip_ahb_mon	AMBA AHB monitor and protocol checker	simulated
of_vip_ahb_bfm	AMBA AHB bus functional model and agent	simulated
of_vip_apb_mon	AMBA APB monitor and protocol checker	simulated
of_vip_apb_bfm	AMBA APB bus functional model and agent	simulated
of_vip_ace_mon	AMBA ACE monitor and protocol checker	planned