IP PortfolioVerification IPamba bus vip

of_vip_chi_bfm

AMBA CHI bus functional model and agent

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3

CHI request node and subordinate node agents with cache state modeling, credit management and transaction sequence library.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
tx_flitoutvalid-qualified bus512 
rx_flitinvalid-qualified bus512 

Standards

  • AMBA CHI

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