IP PortfolioVerification IPamba bus vip
of_vip_apb_mon
AMBA APB monitor and protocol checker
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
APB3/APB4 monitor checking setup and access phase sequencing, PSEL/PENABLE timing, stable address and data during wait states and PSLVERR usage.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 80 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- AMBA APB4
Basis projects
Permissive open projects the implementation may build on.
- cocotbext-axi (MIT)
More in amba bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_axi4_mon | AMBA AXI4 monitor and protocol checker | simulated |
| of_vip_axi4_bfm | AMBA AXI4 bus functional model and agent | simulated |
| of_vip_axil_mon | AMBA AXI4-Lite monitor and protocol checker | simulated |
| of_vip_axil_bfm | AMBA AXI4-Lite bus functional model and agent | simulated |
| of_vip_axis_mon | AMBA AXI4-Stream monitor and protocol checker | simulated |
| of_vip_axis_bfm | AMBA AXI4-Stream bus functional model and agent | simulated |
| of_vip_ahb_mon | AMBA AHB monitor and protocol checker | simulated |
| of_vip_ahb_bfm | AMBA AHB bus functional model and agent | simulated |
| of_vip_apb_bfm | AMBA APB bus functional model and agent | simulated |
| of_vip_ace_mon | AMBA ACE monitor and protocol checker | planned |