IP PortfolioSoC interconnectdebug and trace
of_rv_dm
RISC-V Debug Module
Maturity simulatedTargets FPGA + ASICDifficulty HardPriority 1
Debug module with run control (halt, resume, reset), abstract commands, program buffer, system bus access and multi-hart selection.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| dmi | in | valid-qualified bus | 41 | |
| halt_req | out | parallel | 8 | |
| m_sba | out | valid-qualified bus | 96 |
Standards
- RISC-V Debug Specification 1.0
Basis projects
Permissive open projects the implementation may build on.
- PULP riscv-dbg (SHL-0.51)
- OpenTitan (Apache-2.0)
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |
| of_uart_bus_bridge | UART to bus debug bridge | planned |