IP PortfolioSoC interconnectdebug and trace
of_trace_funnel
Trace funnel, buffer and sink
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Merges trace streams from several sources, stores them in an on-chip circular buffer or routes them to memory or a trace port, with trigger and stop control.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| trace_in | in | AXI4-Stream | 128 | |
| trace_port | out | parallel | 16 | |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
No external standard applies.
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |
| of_uart_bus_bridge | UART to bus debug bridge | planned |