IP PortfolioSoC interconnectdebug and trace
of_jtag_axi
JTAG to AXI4 master bridge
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Lets a host issue AXI4 read and write transactions through the JTAG port for bring-up and memory access without a CPU.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tck | in | clock | 1 | |
| tms | in | serial | 1 | |
| tdi | in | serial | 1 | |
| tdo | out | serial | 1 | |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- IEEE 1149.1
- AMBA AXI4
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_logic_analyzer | Integrated logic analyzer | simulated |
| of_uart_bus_bridge | UART to bus debug bridge | planned |