IP PortfolioSoC interconnectdebug and trace
of_logic_analyzer
Integrated logic analyzer
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
On-chip logic analyzer with configurable probe width and depth, multi-level triggers, pre/post trigger capture and readout over JTAG or the system bus.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| probes | in | parallel | 256 |
Standards
No external standard applies.
More in debug and trace
| ID | Block | Maturity |
|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed |
| of_ijtag_net | IEEE 1687 IJTAG network | planned |
| of_rv_etrace | RISC-V E-Trace encoder | planned |
| of_rv_ntrace | RISC-V N-Trace encoder | planned |
| of_trace_funnel | Trace funnel, buffer and sink | planned |
| of_jtag_axi | JTAG to AXI4 master bridge | planned |
| of_uart_bus_bridge | UART to bus debug bridge | planned |