IP PortfolioSoC interconnectinter-processor communication
of_hw_semaphore
Hardware semaphore bank
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Bank of atomic test-and-set semaphores with owner ID, release interrupts and a lock-timeout watchdog.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in inter-processor communication
| ID | Block | Maturity |
|---|---|---|
| of_mailbox | Inter-processor mailbox | simulated |