IP PortfolioSoC interconnectclock, reset and power control
of_dvfs_ctrl
DVFS controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Dynamic voltage and frequency scaling sequencer that steps PLL settings and regulator voltage requests in a safe order with programmable operating point tables.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pll_cfg | out | parallel | 32 | |
| vid | out | parallel | 8 |
Standards
No external standard applies.
More in clock, reset and power control
| ID | Block | Maturity |
|---|---|---|
| of_clk_div | Integer clock divider (50 % duty) | fpga-routed |
| of_clk_gate | Clock-gating cell model (latch-based ICG) | simulated |
| of_clk_mux_gf | Glitch-free clock multiplexer | simulated |
| of_ccu | Clock control unit | simulated |
| of_rcu | Reset control unit | simulated |
| of_ppu | Power policy unit | simulated |
| of_clk_mon | Clock monitor and frequency meter | planned |