Integer clock divider (50 % duty)

Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1

Divides the input clock by any integer DIV >= 2 with an exact 50 % duty cycle for even and odd ratios (falling-edge phase flop for odd DIV), glitch-free flop-driven output and a matching clock-enable tick.

FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
clk_out	out	clock	1

Standards

No external standard applies.

More in clock, reset and power control

ID	Block	Maturity
of_clk_gate	Clock-gating cell model (latch-based ICG)	simulated
of_clk_mux_gf	Glitch-free clock multiplexer	simulated
of_ccu	Clock control unit	simulated
of_rcu	Reset control unit	simulated
of_ppu	Power policy unit	simulated
of_clk_mon	Clock monitor and frequency meter	planned
of_dvfs_ctrl	DVFS controller	planned