IP PortfolioSoC interconnectclock, reset and power control
of_clk_gate
Clock-gating cell model (latch-based ICG)
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Integrated clock-gating cell model with a transparent-low enable latch and AND gate, plus a test (scan) enable. Glitch-free for enables that change at any time.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| en | in | parallel | 1 | |
| gclk | out | clock | 1 |
Standards
No external standard applies.
More in clock, reset and power control
| ID | Block | Maturity |
|---|---|---|
| of_clk_div | Integer clock divider (50 % duty) | fpga-routed |
| of_clk_mux_gf | Glitch-free clock multiplexer | simulated |
| of_ccu | Clock control unit | simulated |
| of_rcu | Reset control unit | simulated |
| of_ppu | Power policy unit | simulated |
| of_clk_mon | Clock monitor and frequency meter | planned |
| of_dvfs_ctrl | DVFS controller | planned |