Power policy unit

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Power domain sequencer driving power switches, isolation, retention and reset in order for each domain, with handshake to software and wake-up sources; aligned with IEEE 1801 power intent.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
wake	in	parallel	8
pwr_ctrl	out	parallel	32
pwr_ack	in	parallel	8

Standards

IEEE 1801

More in clock, reset and power control

ID	Block	Maturity
of_clk_div	Integer clock divider (50 % duty)	fpga-routed
of_clk_gate	Clock-gating cell model (latch-based ICG)	simulated
of_clk_mux_gf	Glitch-free clock multiplexer	simulated
of_ccu	Clock control unit	simulated
of_rcu	Reset control unit	simulated
of_clk_mon	Clock monitor and frequency meter	planned
of_dvfs_ctrl	DVFS controller	planned