Inter-processor mailbox

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

Multi-channel mailbox with message FIFOs, doorbell interrupts and per-channel ownership for communication between processors or chiplets.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
irq_out	out	parallel	8

Standards

No external standard applies.

More in inter-processor communication

ID	Block	Maturity
of_hw_semaphore	Hardware semaphore bank	planned