IP PortfolioSensing and RFlidar
of_lidar_opa_ctrl
Optical phased array controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Per-emitter phase DAC control and calibration table management for silicon photonic or III-V optical phased array beam steering.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phase_dac | out | parallel | 64 |
Standards
No external standard applies.
More in lidar
| ID | Block | Maturity |
|---|---|---|
| of_lidar_tdc_tof | Pulsed ToF multi-hit TDC | planned |
| of_lidar_spad_readout | SPAD array readout | planned |
| of_lidar_histogram | Time-correlated histogramming engine | simulated |
| of_lidar_fmcw_lin | FMCW LiDAR chirp linearisation | planned |
| of_lidar_fmcw_proc | FMCW LiDAR beat processor | planned |
| of_lidar_laser_drv_905 | 905 nm pulsed laser driver | planned |
| of_lidar_laser_drv_1550 | 1550 nm laser and amplifier driver | planned |
| of_lidar_apd_afe | APD receiver front end | planned |
| of_lidar_mems_mirror_drv | MEMS mirror driver | planned |
| of_lidar_pc_proc | LiDAR point cloud processor | planned |