IP PortfolioSensing and RFlidar
of_lidar_histogram
Time-correlated histogramming engine
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Accumulates photon timestamps across laser shots into per-pixel histograms and extracts peaks, intensity and multiple echoes.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| stamps | in | AXI4-Stream | 32 | |
| returns | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in lidar
| ID | Block | Maturity |
|---|---|---|
| of_lidar_tdc_tof | Pulsed ToF multi-hit TDC | planned |
| of_lidar_spad_readout | SPAD array readout | planned |
| of_lidar_fmcw_lin | FMCW LiDAR chirp linearisation | planned |
| of_lidar_fmcw_proc | FMCW LiDAR beat processor | planned |
| of_lidar_laser_drv_905 | 905 nm pulsed laser driver | planned |
| of_lidar_laser_drv_1550 | 1550 nm laser and amplifier driver | planned |
| of_lidar_apd_afe | APD receiver front end | planned |
| of_lidar_mems_mirror_drv | MEMS mirror driver | planned |
| of_lidar_pc_proc | LiDAR point cloud processor | planned |
| of_lidar_opa_ctrl | Optical phased array controller | planned |