IP PortfolioSensing and RFlidar

of_lidar_pc_proc

LiDAR point cloud processor

Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2

Spherical to Cartesian conversion, ground removal, voxel downsampling and intensity calibration of LiDAR returns.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
returnsinAXI4-Stream64 
pointsoutAXI4-Stream128 

Standards

No external standard applies.

More in lidar

IDBlockMaturity
of_lidar_tdc_tofPulsed ToF multi-hit TDCplanned
of_lidar_spad_readoutSPAD array readoutplanned
of_lidar_histogramTime-correlated histogramming enginesimulated
of_lidar_fmcw_linFMCW LiDAR chirp linearisationplanned
of_lidar_fmcw_procFMCW LiDAR beat processorplanned
of_lidar_laser_drv_905905 nm pulsed laser driverplanned
of_lidar_laser_drv_15501550 nm laser and amplifier driverplanned
of_lidar_apd_afeAPD receiver front endplanned
of_lidar_mems_mirror_drvMEMS mirror driverplanned
of_lidar_opa_ctrlOptical phased array controllerplanned