IP PortfolioDatapath and DSPerror control coding
of_interleaver
Block and convolutional interleaver
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Row-column block interleaver and Forney convolutional interleaver/deinterleaver with configurable depth, backed by single-port or two-port RAM.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | AXI4-Stream | 16 | |
| m_out | out | AXI4-Stream | 16 |
Standards
No external standard applies.
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_crc | Parallel CRC | fpga-routed |
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_ecc_dec | Hamming / SECDED decoder | simulated |
| of_parity | Parity generator and checker | planned |
| of_bch_codec | BCH encoder and decoder | planned |
| of_rs_codec | Reed-Solomon encoder and decoder | planned |
| of_ldpc_dec | LDPC encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned |