IP PortfolioDatapath and DSPerror control coding
of_rs_codec
Reed-Solomon encoder and decoder
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Parametric RS(n,k) over GF(2^m) with systematic encoder and decoder (syndrome, Berlekamp-Massey or Euclid, Chien, Forney), including the RS(528,514) and RS(544,514) Ethernet FEC codes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | AXI4-Stream | 80 | |
| m_out | out | AXI4-Stream | 80 |
Standards
- IEEE 802.3
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_crc | Parallel CRC | fpga-routed |
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_ecc_dec | Hamming / SECDED decoder | simulated |
| of_parity | Parity generator and checker | planned |
| of_bch_codec | BCH encoder and decoder | planned |
| of_ldpc_dec | LDPC encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned |