IP PortfolioDatapath and DSPerror control coding
of_parity
Parity generator and checker
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Even/odd parity generation and checking per byte or per configurable bit group, combinational.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 64 | |
| par | out | parallel | 8 |
Standards
No external standard applies.
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_crc | Parallel CRC | fpga-routed |
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_ecc_dec | Hamming / SECDED decoder | simulated |
| of_bch_codec | BCH encoder and decoder | planned |
| of_rs_codec | Reed-Solomon encoder and decoder | planned |
| of_ldpc_dec | LDPC encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned |