IP PortfolioDatapath and DSPerror control coding
of_crc
Parallel CRC
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Parallel CRC generator/checker for any polynomial (Rocksoft model: POLY, INIT, REFIN, REFOUT, XOROUT) absorbing DATA_WIDTH bits per clock. Presets in the datasheet: CRC-8, CRC-16/CCITT-FALSE, CRC-32 (default), CRC-32C.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | valid-qualified bus | 64 | |
| crc | out | parallel | 32 |
Standards
No external standard applies.
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_ecc_dec | Hamming / SECDED decoder | simulated |
| of_parity | Parity generator and checker | planned |
| of_bch_codec | BCH encoder and decoder | planned |
| of_rs_codec | Reed-Solomon encoder and decoder | planned |
| of_ldpc_dec | LDPC encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned |