IP PortfolioDatapath and DSPerror control coding
of_viterbi
Convolutional encoder and Viterbi decoder
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Rate 1/2 and 1/3 convolutional encoder with puncturing, and soft-decision Viterbi decoder with configurable constraint length (K=3 to 9) and traceback depth.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| llr | in | AXI4-Stream | 16 | |
| m_out | out | AXI4-Stream | 8 |
Standards
- IEEE 802.11
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_crc | Parallel CRC | fpga-routed |
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_ecc_dec | Hamming / SECDED decoder | simulated |
| of_parity | Parity generator and checker | planned |
| of_bch_codec | BCH encoder and decoder | planned |
| of_rs_codec | Reed-Solomon encoder and decoder | planned |
| of_ldpc_dec | LDPC encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned |