IP PortfolioVerification IPserial peripheral vip
of_vip_xspi_mon
Quad/Octal SPI (xSPI) monitor and protocol checker
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Quad and octal SPI monitor decoding command, address, mode, dummy and data phases in SDR and DTR, with DQS timing checks.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 11 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- JEDEC JESD251
More in serial peripheral vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_i2c_mon | I2C monitor and protocol checker | simulated |
| of_vip_i2c_bfm | I2C bus functional model and agent | simulated |
| of_vip_i3c_mon | MIPI I3C monitor and protocol checker | planned |
| of_vip_i3c_bfm | MIPI I3C bus functional model and agent | planned |
| of_vip_spi_mon | SPI monitor and protocol checker | simulated |
| of_vip_spi_bfm | SPI bus functional model and agent | simulated |
| of_vip_xspi_bfm | Quad/Octal SPI host agent and flash model | simulated |
| of_vip_uart_mon | UART monitor and protocol checker | simulated |
| of_vip_uart_bfm | UART bus functional model and agent | simulated |