IP PortfolioVerification IPserial peripheral vip
of_vip_i2c_bfm
I2C bus functional model and agent
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
I2C controller and target agents with 7/10-bit addressing, clock stretching, multi-controller arbitration, SMBus PEC and glitch injection.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| scl | inout | serial | 1 | |
| sda | inout | serial | 1 |
Standards
- NXP UM10204 I2C-bus specification
- SMBus 3.2
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|---|---|---|
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| of_vip_i3c_bfm | MIPI I3C bus functional model and agent | planned |
| of_vip_spi_mon | SPI monitor and protocol checker | simulated |
| of_vip_spi_bfm | SPI bus functional model and agent | simulated |
| of_vip_xspi_mon | Quad/Octal SPI (xSPI) monitor and protocol checker | simulated |
| of_vip_xspi_bfm | Quad/Octal SPI host agent and flash model | simulated |
| of_vip_uart_mon | UART monitor and protocol checker | simulated |
| of_vip_uart_bfm | UART bus functional model and agent | simulated |