IP PortfolioVerification IPserial peripheral vip
of_vip_xspi_bfm
Quad/Octal SPI host agent and flash model
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
xSPI host agent and serial NOR flash model with SFDP tables, status registers, erase/program timing and XIP read modes.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| sclk | out | serial | 1 | |
| dq | inout | parallel | 8 | |
| dqs | inout | serial | 1 | |
| csn | out | serial | 1 |
Standards
- JEDEC JESD251
More in serial peripheral vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_i2c_mon | I2C monitor and protocol checker | simulated |
| of_vip_i2c_bfm | I2C bus functional model and agent | simulated |
| of_vip_i3c_mon | MIPI I3C monitor and protocol checker | planned |
| of_vip_i3c_bfm | MIPI I3C bus functional model and agent | planned |
| of_vip_spi_mon | SPI monitor and protocol checker | simulated |
| of_vip_spi_bfm | SPI bus functional model and agent | simulated |
| of_vip_xspi_mon | Quad/Octal SPI (xSPI) monitor and protocol checker | simulated |
| of_vip_uart_mon | UART monitor and protocol checker | simulated |
| of_vip_uart_bfm | UART bus functional model and agent | simulated |