IP PortfolioVerification IPserial peripheral vip
of_vip_uart_bfm
UART bus functional model and agent
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
UART transmitter and receiver agent with configurable baud, data bits, parity, stop bits, RTS/CTS flow control and baud error injection.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| txd | out | serial | 1 | |
| rxd | in | serial | 1 | |
| rts | out | serial | 1 | |
| cts | in | serial | 1 |
Standards
- TIA-232-F
More in serial peripheral vip
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|---|---|---|
| of_vip_i2c_mon | I2C monitor and protocol checker | simulated |
| of_vip_i2c_bfm | I2C bus functional model and agent | simulated |
| of_vip_i3c_mon | MIPI I3C monitor and protocol checker | planned |
| of_vip_i3c_bfm | MIPI I3C bus functional model and agent | planned |
| of_vip_spi_mon | SPI monitor and protocol checker | simulated |
| of_vip_spi_bfm | SPI bus functional model and agent | simulated |
| of_vip_xspi_mon | Quad/Octal SPI (xSPI) monitor and protocol checker | simulated |
| of_vip_xspi_bfm | Quad/Octal SPI host agent and flash model | simulated |
| of_vip_uart_mon | UART monitor and protocol checker | simulated |