IP PortfolioSoC interconnectclock domain crossing
of_sync_bit
Multi-flop bit synchronizer
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Two-, three- or four-flop level synchronizer for single-bit (or independent / Gray-coded multi-bit) signals crossing into the clk domain, with configurable reset value and FPGA ASYNC_REG attributes.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| d | in | parallel | 1 | |
| q | out | parallel | 1 |
Standards
No external standard applies.
More in clock domain crossing
| ID | Block | Maturity |
|---|---|---|
| of_sync_bus | Multi-bit bus synchronizer (handshake) | fpga-routed |
| of_sync_handshake | Four-phase req/ack handshake synchronizer | simulated |
| of_sync_pulse | Toggle pulse synchronizer | simulated |
| of_sync_reset | Reset synchronizer | simulated |