IP PortfolioSoC interconnectclock domain crossing
of_sync_handshake
Four-phase req/ack handshake synchronizer
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Return-to-zero request/acknowledge handshake between asynchronous clock domains with a valid/ready source port, a load strobe and valid/ready destination port, and a source-side completion pulse. Only single-bit levels cross (through of_sync_bit), so it is safe for any clock ratio.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| src_clk | in | clock | 1 |
Standards
No external standard applies.
More in clock domain crossing
| ID | Block | Maturity |
|---|---|---|
| of_sync_bit | Multi-flop bit synchronizer | fpga-routed |
| of_sync_bus | Multi-bit bus synchronizer (handshake) | fpga-routed |
| of_sync_pulse | Toggle pulse synchronizer | simulated |
| of_sync_reset | Reset synchronizer | simulated |