IP PortfolioSoC interconnectclock domain crossing
of_sync_pulse
Toggle pulse synchronizer
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Transfers single-cycle pulses between asynchronous clock domains with a source toggle flop, a 2-4 flop synchronizer and a destination edge detector; a synchronized feedback toggle gives a src_busy flag that guarantees no lost or duplicated pulses for any clock ratio.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| pulse_in | in | parallel | 1 | |
| pulse_out | out | parallel | 1 | |
| src_clk | in | clock | 1 |
Standards
No external standard applies.
More in clock domain crossing
| ID | Block | Maturity |
|---|---|---|
| of_sync_bit | Multi-flop bit synchronizer | fpga-routed |
| of_sync_bus | Multi-bit bus synchronizer (handshake) | fpga-routed |
| of_sync_handshake | Four-phase req/ack handshake synchronizer | simulated |
| of_sync_reset | Reset synchronizer | simulated |