IP PortfolioSoC interconnectregister blocks
of_wb_regs
Wishbone B4 slave register block
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Wishbone B4 classic slave register block (32-bit port, byte select) with registered ACK / ERR; the register map comes from a register-map specification (openforge.iplib.regmap).
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | Wishbone control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| hw_in | in | parallel | 32 | |
| hw_out | out | parallel | 32 |
Standards
- Wishbone B4
More in register blocks
| ID | Block | Maturity |
|---|---|---|
| of_regbank | Register bank core (register-map driven) | simulated |
| of_apb_regs | APB slave register block | fpga-routed |
| of_axil_regs | AXI4-Lite slave register block | simulated |