AXI4-Lite to APB bridge

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

AXI4-Lite slave to APB4 master bridge with PSTRB and PPROT mapping, multiple APB slave selects and PSLVERR to SLVERR mapping.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
s_axil	in	valid-qualified bus	128
m_apb	out	valid-qualified bus	64

Standards

AMBA AXI4-Lite
AMBA APB4

More in bus bridges and converters

ID	Block	Maturity
of_ahb2apb	AHB-Lite to APB bridge	simulated
of_axi4_to_axil	AXI4 to AXI4-Lite converter	simulated
of_axi4_to_ahb	AXI4 to AHB bridge	planned
of_ahb_to_axi4	AHB to AXI4 bridge	planned
of_axi4_cdc	AXI4 clock-domain crossing bridge	simulated
of_apb_cdc	APB clock-domain crossing bridge	simulated
of_axi4_to_axis	AXI4 memory-mapped to stream bridge	planned