IP PortfolioSoC interconnectbus bridges and converters
of_axi4_cdc
AXI4 clock-domain crossing bridge
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Asynchronous AXI4 bridge using one dual-clock FIFO per channel with Gray-coded pointers, independent depths per channel and reset isolation.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_axi | in | valid-qualified bus | 256 | AXI4 slave port (AW/W/AR channels) |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
| m_clk | in | clock | 1 |
Standards
- AMBA AXI4
Basis projects
Permissive open projects the implementation may build on.
- PULP AXI (SHL-0.51)
- verilog-axi (MIT)
More in bus bridges and converters
| ID | Block | Maturity |
|---|---|---|
| of_ahb2apb | AHB-Lite to APB bridge | simulated |
| of_axi4_to_axil | AXI4 to AXI4-Lite converter | simulated |
| of_axil_to_apb | AXI4-Lite to APB bridge | simulated |
| of_axi4_to_ahb | AXI4 to AHB bridge | planned |
| of_ahb_to_axi4 | AHB to AXI4 bridge | planned |
| of_apb_cdc | APB clock-domain crossing bridge | simulated |
| of_axi4_to_axis | AXI4 memory-mapped to stream bridge | planned |