IP PortfolioSoC interconnectbus bridges and converters
of_ahb_to_axi4
AHB to AXI4 bridge
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
AHB5 slave to AXI4 master bridge with optional write buffering and burst conversion, for connecting MCU-class cores to AXI4 fabrics.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_ahb | in | valid-qualified bus | 96 | |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA AXI4
- AMBA AHB5
More in bus bridges and converters
| ID | Block | Maturity |
|---|---|---|
| of_ahb2apb | AHB-Lite to APB bridge | simulated |
| of_axi4_to_axil | AXI4 to AXI4-Lite converter | simulated |
| of_axil_to_apb | AXI4-Lite to APB bridge | simulated |
| of_axi4_to_ahb | AXI4 to AHB bridge | planned |
| of_axi4_cdc | AXI4 clock-domain crossing bridge | simulated |
| of_apb_cdc | APB clock-domain crossing bridge | simulated |
| of_axi4_to_axis | AXI4 memory-mapped to stream bridge | planned |