IP PortfolioSoC interconnectbus bridges and converters
of_ahb2apb
AHB-Lite to APB bridge
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
AHB-Lite slave to APB4 master bridge (32-bit data): each AHB transfer becomes one APB transfer with PSTRB from HSIZE/HADDR, PPROT from HPROT, APB wait states stretched via HREADYOUT and PSLVERR mapped to the two-cycle AHB ERROR response; pipelined address phases are accepted.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AHB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| m_apb | out | valid-qualified bus | 64 |
Standards
- AMBA AHB5
- AMBA APB4
More in bus bridges and converters
| ID | Block | Maturity |
|---|---|---|
| of_axi4_to_axil | AXI4 to AXI4-Lite converter | simulated |
| of_axil_to_apb | AXI4-Lite to APB bridge | simulated |
| of_axi4_to_ahb | AXI4 to AHB bridge | planned |
| of_ahb_to_axi4 | AHB to AXI4 bridge | planned |
| of_axi4_cdc | AXI4 clock-domain crossing bridge | simulated |
| of_apb_cdc | APB clock-domain crossing bridge | simulated |
| of_axi4_to_axis | AXI4 memory-mapped to stream bridge | planned |