of_dsp_vliw
VLIW DSP core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Four to eight slot VLIW DSP with SIMD MAC units, zero-overhead loops, circular and bit-reversed addressing and a compiler-visible register file.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- IEEE 754-2019
More in dsp
| ID | Block | Maturity |
|---|---|---|
| of_dsp_audio | Audio DSP core | planned |
| of_dsp_baseband | Baseband DSP core | planned |
| of_dsp_vision | Vision DSP core | planned |
| of_dsp_radar | Radar signal processing DSP | planned |
| of_dsp_motor_control | Motor control coprocessor | planned |
| of_dsp_sensor_hub | Sensor fusion DSP | planned |