of_dsp_radar
Radar signal processing DSP
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
DSP with instructions for FFT butterflies, complex magnitude, CFAR windows and angle estimation for FMCW radar processing chains.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| adc_in | in | AXI4-Stream | 64 |
Standards
No external standard applies.
More in dsp
| ID | Block | Maturity |
|---|---|---|
| of_dsp_vliw | VLIW DSP core | planned |
| of_dsp_audio | Audio DSP core | planned |
| of_dsp_baseband | Baseband DSP core | planned |
| of_dsp_vision | Vision DSP core | planned |
| of_dsp_motor_control | Motor control coprocessor | planned |
| of_dsp_sensor_hub | Sensor fusion DSP | planned |