of_dsp_baseband
Baseband DSP core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Wide SIMD DSP with complex multiply-accumulate, saturating arithmetic and a vector memory for wireless physical layer processing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| iq_in | in | AXI4-Stream | 64 | |
| iq_out | out | AXI4-Stream | 64 |
Standards
- 3GPP TS 38.211
- IEEE 802.11ax
More in dsp
| ID | Block | Maturity |
|---|---|---|
| of_dsp_vliw | VLIW DSP core | planned |
| of_dsp_audio | Audio DSP core | planned |
| of_dsp_vision | Vision DSP core | planned |
| of_dsp_radar | Radar signal processing DSP | planned |
| of_dsp_motor_control | Motor control coprocessor | planned |
| of_dsp_sensor_hub | Sensor fusion DSP | planned |