IP PortfolioProcessorsriscv_safety
of_cpu_safety_island
Safety island subsystem
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Self-contained lockstep RV32 subsystem with ECC SRAM, watchdogs, fault collection unit and isolated clock and reset that monitors the main SoC.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| fault_in | in | parallel | 64 | |
| safe_state | out | parallel | 8 |
Standards
- ISO 26262
- IEC 61508
More in riscv_safety
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_lockstep | Dual-core lockstep RV32 safety core | planned |
| of_cpu_rv64_lockstep | Lockstep RV64 application core | planned |
| of_cpu_lockstep_checker | Lockstep comparator and delay unit | simulated |