IP PortfolioProcessorsriscv_safety
of_cpu_rv32_lockstep
Dual-core lockstep RV32 safety core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
RV32IMC core pair running in delayed lockstep with output comparison, ECC on register file and TCMs, and a fault signalling interface to the system error manager.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| fault_out | out | parallel | 4 |
Standards
- RISC-V RV32IMC
- ISO 26262
- IEC 61508
Notes
Targets ASIL D architectural metrics; safety manual and FMEDA are deliverables.
More in riscv_safety
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv64_lockstep | Lockstep RV64 application core | planned |
| of_cpu_lockstep_checker | Lockstep comparator and delay unit | simulated |
| of_cpu_safety_island | Safety island subsystem | planned |