IP PortfolioProcessorsriscv_safety
of_cpu_lockstep_checker
Lockstep comparator and delay unit
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Core-agnostic lockstep checker with configurable temporal diversity delay, output comparison, error injection for self-test and fault reporting.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| main_out | in | parallel | 256 | |
| shadow_out | in | parallel | 256 | |
| mismatch | out | serial | 1 |
Standards
- ISO 26262
- IEC 61508
More in riscv_safety
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_lockstep | Dual-core lockstep RV32 safety core | planned |
| of_cpu_rv64_lockstep | Lockstep RV64 application core | planned |
| of_cpu_safety_island | Safety island subsystem | planned |