IP PortfolioProcessorsriscv_safety
of_cpu_rv64_lockstep
Lockstep RV64 application core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
RV64GC application core with split-lock operation (lockstep or two independent cores) for automotive domain controllers running a hypervisor or POSIX RTOS.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| fault_out | out | parallel | 4 |
Standards
- RISC-V RV64GC
- ISO 26262
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_safety
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_lockstep | Dual-core lockstep RV32 safety core | planned |
| of_cpu_lockstep_checker | Lockstep comparator and delay unit | simulated |
| of_cpu_safety_island | Safety island subsystem | planned |