IP PortfolioProcessorsriscv_vector
of_cpu_rvv_unit
RISC-V vector unit
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
Decoupled vector coprocessor implementing RVV 1.0 with a configurable number of lanes and VLEN, attached to a scalar RV64 core.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| vinsn | in | valid-qualified bus | 64 | |
| vresult | out | valid-qualified bus | 64 |
Standards
- RISC-V Vector 1.0
More in riscv_vector
| ID | Block | Maturity |
|---|---|---|
| of_cpu_zve32_embedded_vector | Embedded vector extension unit | planned |
| of_cpu_rv64gcv_app | RV64GCV in-order core with integrated vector | planned |